Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
نویسندگان
چکیده
This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-centered 6T SRAM cells. key words: SRAM, soft error rate (SER), multiple cell upset (MCU), neutron particle, twin well, triple well
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ورودعنوان ژورنال:
- IEICE Transactions
دوره 96-A شماره
صفحات -
تاریخ انتشار 2013